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Shukla, Sankalp
- PULSE WIDTH MODULATOR USING OTRA BASED TIMER CIRCUIT
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College., IN
2 4Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science., IN
1 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College., IN
2 4Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science., IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 2 (2022), Pagination: 1358-1362Abstract
This paper proposes a modified PWM circuit using OTRA based analog timer circuit. Designing a pulse width modulator circuit by employing the proposed analog timer circuit results in a waveform having variable duty cycle and time period. The timer circuit consists of comparators designed using OTRA and flip flops. The fabrication of timer circuit on a monolithic integrated circuit is easier as the carrier signal type is exponential and no additional circuitry is needed unlike for triangular and sawtooth pulses. The process parameters of 0.5 µm CMOS have been used for performing an intensive simulation of the proposed PWM circuit.Keywords
Timer Circuit, Pulse Width Modulator (PWM), OTRA, Flip-FlopReferences
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- Controlling Ambipolar Current And Enhancement Of On-state Current With High And Low Concentration Source Pockets
Abstract Views :103 |
PDF Views:1
Authors
Sudhan Kumar
1,
Dheeraj Singh Rajput
2,
Ritu Gupta
2,
Sankalp Shukla
2,
Deep Kishore Parsediya
3,
Vikash Sharma
4
Affiliations
1 Department of Electronics and Communication Engineering, National Institute of Technology, Goa, IN
2 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College, IN
3 Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science, IN
4 Department of Electronics and Communication Engineering, Rewa Engineering College, IN
1 Department of Electronics and Communication Engineering, National Institute of Technology, Goa, IN
2 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College, IN
3 Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science, IN
4 Department of Electronics and Communication Engineering, Rewa Engineering College, IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 1 (2022), Pagination: 1288-1294Abstract
This paper proposes and investigates a new architecture of PNPN TFET by using 2-D ATLAS Device Simulation Software TCAD Tool. The source pocket plays a crucial role in increasing the ON-state current through Tunnel FET. In order to enhance the source pocket characteristics, the source pocket is divided laterally into high and low concentration source pockets without modulating its width (LP). This modification results in a reduction of tunnelling width (λ), thereby increasing the significant amount of lateral electric field and suppressing the horizontal electric field, which in turn enhances the tunnelling probability as well as tunnelling rate. This proposed structure is a promising candidate for getting higher ON-state current (Ion), higher current ratio (Ion/Ioff), lower threshold voltage (VT) and reduced steepness sub-threshold slope (SS). These parameters are calculated with respect to conventional PNPN TFET and hetero-dielectric BOX (HDB) PNPN TFET, which enable the device to be operated efficiently with lower power consumption.Keywords
Band-to-Band Tunnelling (BTBT), Sub-Threshold Swing, Tunnelling Field-Effect Transistor (TFET), High-κ Dielectric, Hetero-Dielectric BOX (HDB)References
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